1. Field
Example embodiments relate to semiconductor devices and dynamic random access memory (DRAM) devices, and more particularly, to semiconductor devices and dynamic random access memory (DRAM) devices including a buried gate pattern. Some example embodiments include a buried gate pattern with a capping layer pattern of a high-k material layer, which has a dielectric constant of more than about 10.
2. Related Art
As semiconductor devices have become highly integrated, it is hard to obtain a stable operation of a transistor. As a way of resolving short channel effects and reducing a size of a transistor, a recess channel array transistor (RCAT) was realized.
In a RCAT, a gate electrode protrudes toward (or from) the top of a semiconductor substrate. In this case, due to the protruding gate electrode, it makes processes such as contact plug formation and planarization processes more difficult. Moreover, the edge portion of a depressed channel region causes leakage current, which is generated due to a field crowding effect. Furthermore, forming the protruding gate electrode requires a high-level patterning process.
In order to resolve the above limitations, a buried channel array transistor (BCAT) is being continuously studied. In the BCAT, a gate electrode is formed buried inside a semiconductor substrate. A capping layer pattern is provided on the buried gate electrode. The upper surface of the capping layer pattern and the upper surface of the semiconductor substrate are formed at the same level (or height). That is, the buried gate electrode is provided at a lower level than the top surface of the semiconductor substrate because of the capping layer pattern. Source/drain regions are provided in the semiconductor substrate at both sides of the buried gate electrode.
Moreover, the source/drain regions are electrically connected to a bit line and a storage electrode of a capacitor, and thus their upper regions require impurity doping of a high concentration for ohmic contact. On the contrary, a channel region of the buried gate electrode is formed with a low impurity concentration for application of a metal gate electrode. In the buried gate electrode structure, if a doping concentration of the upper region is enhanced in order to reduce the resistance of the source/drain regions, junction leakage current of the source/drain regions is increased due to an increase in the electric field. Accordingly, an appropriate amount of impurity doping is required in order to form the source/drain regions. In this case, resistance is partially increased at the source/drain regions adjacent to the capping layer pattern. An increase in resistance of the source/drain regions deteriorates the current attribute of a transistor, for example, current drivability.